There have been known flexible printed circuit boards (FPC) in which a polyimide film is used as an insulating layer material having a high heat resistance, high electrically insulation performance, and high bending tenacity (Japanese Patent Published Application No. Hei 10-209593). Also, there have been developed FPCs in which FPCs are multilayered and formed with interlayer interconnection via through halls.
In the case of a multilayered FPC with through halls, it is impossible to mount a chip on a through hall to decrease the flexibility of designing circuit layouts due to the restriction on the location of the interlayer interconnection. Therefore, there is a definite ceiling to the implementation density, and it is impossible to meet the demands for high density packaging.
In order to cope with this situation, there has been resin multilayer printed circuit boards developed in which via-on-via is possible by interlayer interconnection via IVH (Interstitial Via Hole) in place of a through hall, for example, ALIVH (Any Layer Interstitial Via Hole) of Matsushita Electric Industrial Co., Ltd, or polyimide composite multilayer build up integrated circuit board (MOSAIC) of Sony Chemicals Corporation in which polyimide FPCs are built up in a multilayered structure without using a through hall (for example, refer to Japanese Patent Published Application No. Hei 06-268345 and Japanese Patent Published Application No. Hei 07-147464).
Also, proposed in Japanese Patent Application No. 2001-85224 assigned to the same assignee as the assignee of this application is a structure and a manufacturing method for obtaining a multilayered FPC having an IVH structure in accordance with a simple process making use of starting items of general purpose copper plated resin substrate components (copper plated polyimide substrate components) each of which is composed of a polyimide film as an insulating layer with a conductive layer of copper foil being attached to one of the surfaces thereof.
In the multilayer wiring board assembly component as proposed in Japanese Patent Application No. 2001-85224, an IVH structure is formed as illustrated in FIG. 1 in which, after opening a through hole in a copper plated resin film with a copper foil being attached to one surface of the insulating layer thereof, a conductive resin composition (a resin base conductive paste) is applied to fill the through hole from the copper foil side by a printing technique such as screen printing and the like. Meanwhile, in FIG. 1, numeral 1 designates an insulating layer; numeral 2 designates a copper foil member; numeral 4 designates a through hole; and numeral 5 designates a conductive resin composition with which the through hole 4 is filled.
Particularly, by designing the bore diameter of the opening of a mask (stencil) used during screen printing to be larger than the bore diameter of the IVH, there becomes available a margin in alignment during screen printing to some extent while a head shaped projection 5A is formed on the copper foil member 2 by the conductive resin composition 5 with a diameter corresponding to the bore diameter of the mask opening so that it is possible to increase the contact area between the copper foil member 2 and the conductive resin composition 5 filling the through hole 4. Also, it is possible to prevent the conductive resin composition 5 filling the through hole 4 from falling out from the through hole 4 by the existence of the head shaped projection 5A.
Furthermore, disclosed as a similar technique are a structure and a manufacturing method for obtaining an IVH multilayer substrate by one time lamination making use of starting items of general purpose copper plated resin substrate components each of which is composed of a polyimide film as an insulating layer with a conductive layer of copper foil being attached to one of the surfaces thereof (for example, disclosed in Shoji Ito and other three, “IVH Multilayer Substrate Laminated In Bulk With Polyimide Substrates Having Copper Foil”, pp. 31 to 32 (Mar. 18, 2002), Japan Institute of Electronics Packaging 16th Microelectronics Show).
In this case, as illustrated in FIG. 2, the IVH structure of the IVH multilayer substrate laminated in bulk with polyimide substrates having copper foil is formed after opening a through hole (via hole 13) in a copper plated resin film with a copper foil 12 attached to one surface of an insulating layer (polyimide substrate) 11, a resin base conductive paste 14 is applied to fill the through hole by a printing technique such as screen printing and the like from the copper foil 12.
In accordance with this type of IVH multilayer substrate, it is possible to increase the margin in alignment during screen printing to some extent, to form a brim member 15 on the copper foil member 12 by using the conductive paste 14 with a diameter corresponding to the bore diameter of the mask opening so that it is possible to increase the contact area between the copper foil member 12 and the conductive paste 14 filling the through hole 4.
Furthermore, for example, the technique as illustrated in FIG. 3 is also provided (Japanese Patent Published Application No. Hei 9-828325).
However, in the case of the multilayer wiring board assembly component as proposed in Japanese Patent Application 2001-85224, when lamination adhesion is performed for multilayering after hardening the conductive resin composition 5, because of the thickness of the conductive resin composition 5 (the head shaped projection 5A) located above the copper foil, it is necessary to form the adhesive layer with sufficient thickness to accept the electrode thickness of the copper foil and the thickness of the conductive resin composition 5 (the head shaped projection 5A) located above the copper foil. The smoothness of the surface of the multilayer wiring board assembly degrades unless a thicker adhesive layer is used.
Because of this, in the case of the general purpose copper plated resin substrate components, each of which is composed of a polyimide film as an insulating layer with a conductive layer of copper foil being attached to one of the surfaces thereof, it is necessary to form an adhesive layer having a thickness of the order of 15 to 30 μm when the insulating layer has a thickness of the order of 15 to 30 μm and the copper foil has a thickness of the order of 5 to 20 μm, resulting in increasing the thickness of the substrate due to the increased thickness of the adhesive layer. This problem is true in the case of the IVH multilayer substrate as illustrated in FIG. 2.
On the other hand, in order to make close contact between the conductive resin composition and the copper foil of an adjacent layer, it is suggested to laminate the conductive resin composition in a soft condition before hardening.
However, if this technique is applied to the structure as proposed in Japanese Patent Application No. 2001-85224, a portion of the conductive resin composition 5 (the head shaped projection 5A) located above the copper foil 2 is excessively squashed and extended as illustrated in FIG. 4 under the lamination pressure P during multilayer lamination so that it is difficult to make the dimensions of the respective head shaped projection 5A even, as seen from the surface of the substrate, therefore, in addition to this, a short-circuit would be formed. This problem is also true in the case of the IVH multilayer substrate as illustrated in FIG. 2.
The present invention has been made in light of the circumstances described above. It is an object of the present invention to provide a multilayer wiring board assembly component and a manufacturing method thereof and a multilayer wiring board assembly in which the multilayer wiring board assembly can be made thin without compromising the contact reliability between a conductive resin composition and a conductive circuit member and without compromising the smoothness of the substrate.
Also, it is another object of the present invention to provide a multilayer wiring board assembly component and a manufacturing method thereof and a multilayer wiring board assembly in which film peeling or separation does not occur even if a reliability test is carried out by exposure to a high temperature while the contact area between the conductive circuit member and the conductive paste filling a via hole can be increased.
On the other hand, along with the increasing density of circuitry, the implementation practice of electric elements on the printed circuit board tends to be shifted from those based on the wire bonding technique to those based on the flip chip implementation by means of the bump connection using electrodes formed on the bottom surface of a chip. The flip chip implementation is an implementation technique for making electric connection in bulk by providing conductive bumps (projections) 2 on the surface of a substrate located opposite to a chip 1, and mounting the chip 1 on the substrate 3 in order so that the chip electrodes 4 are located opposite to substrate electrodes 5 through the bumps 2 as illustrated in FIG. 5.
There have been known several implementation techniques for the flip chip implementation such as a technique that makes use of solder bumps for making connection between a chip and a circuit board, a technique that makes use of a conductive adhesive for making connection, a technique that makes use of gold (Au) for making connection between a chip and a circuit board and so forth (“Electronic Industry Material”, vol. 39, No. 9, September, 2000, Kogyo Chosakai Publishing Co., Ltd. as published in Sep. 1, 2000, pp. 36 to 40).
In the case of the flip chip implementation that makes use of solder bumps for making connection, there is a problem in that the chip may be disconnected from the substrate due to stress generated at the connection interface between the substrate and the chip by mechanical shock or heat as generated by the operation of the chip. This causes the bump connection method to lose it's advantage over the wire bonding technique.
In the case of the flip chip implementation that makes use of solder bumps for making connection, it is estimated that the disconnection of the chip from the substrate starts from the slenderest portion of the bump by the shearing stress between the bump and the substrate electrode due to the differential coefficient of thermal expansion between the bump and the substrate electrode (pad member). This estimation has been confirmed by simulation on the basis of the finite element method.
As illustrated in the expanded view of FIG. 6, in the case of the bump 2 of a solder ball connected to a flat pad (substrate electrode) 5, a locally deformed portion A forms at the boundary surface between the bump 5 and the pad 5 where the stress is concentrated so that destruction is likely at this location. Namely, defects due to contact between different materials are concentrated at the boundary surface therebetween at which a mechanically fragile composition layer of tin and copper is segregated and which is estimated to be the starting point of destruction.
In the case of the technique that makes use of solder bumps, while a self alignment effect is known as automatic alignment of a chip with a substrate by solder wetting on the electrode during the reflow process for melting the solder, the self alignment effect can not be expected in the case of gold bumps so it is difficult to align a chip to a substrate.
Accordingly, it is another objective of the present invention to provide a printed circuit board and a manufacturing method thereof for mounting a flip chip in which the reliability of connection between a chip and a substrate with the self alignment effect, can be expected even in the case of gold bumps.